cpu
logisim
Overview
A single-cycle 16-bit RISC processor core implemented in Logisim Evolution. This project includes a fully custom ALU, register file, control logic, memory interface, and support for I/O using the TTY and keyboard components.
Features
Word-addressed memory (16-bit wide)
8 general-purpose registers ($r0–$r7), with $r0 hardwired to zero and $r7 used as a link register
R, I, and J-type instruction formatsSupport for immediate values (with sign-extension)
Full support for branching and jumping
Input (keyboard) and output (TTY) I/O instructions
Asynchronous reset support
Logisim memory latch integration for realistic RAM timing
Compliant with the automated test framework and Logisim component restrictions
Computer Architecture
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